Celestial AI raises $250M for its optical interconnect technology
Celestial AI Inc., a startup that develops optical technology for linking chips, has raised $250 million in funding at a $2.5 ...
Arteris Selected by Nextchip to Accelerate Chip Designs for Automotive Vision Technology
Arteris’ FlexNoC network-on-chip (NoC) interconnect IP with the Functional Safety option provides Nextchip with optimal flexibility and superior ...
Photon-shuttling interconnection device enables direct communication among multiple quantum processors
Quantum computers have the potential to solve complex problems that would be impossible for the most powerful classical ...
2D Graphene Interconnects For CMOS And Integrated Circuits
Inventor Bellezza Has Several US Patents for Fusing Circuits Using Low Temperatures Within The Thermo Budget of CMOS Chips, It is a Single Step Proce ...
Arteris selected by Nextchip to accelerate chip designs
Arteris (AIP) announced that Nextchip has licensed Arteris’ FlexNoC 5 interconnect IP with Functional Safety for their EFREET1 project for ...
Stocktwits on MSN4d
Astera Labs Stock Loses Steam On Reportedly Missing Out On Supplying Retimers For Nvidia's Next-Gen Blackwell Chip: Retail's Bearish
Shares of Astera Labs Inc. (ALAB) shed their intraday gains of nearly 2.5% on Wednesday to end the day flat after a report ...
Design-Reuse14d
High speed NoC (Network On-Chip) Interconnect IP
OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OIC is the ORBIT high-speed On-chip Interconnect, which delivers exceptional performance ...
Semiconductor Engineering2d
Potential of AOS Memories As A High-Performance SRAM Substitute (Georgia Tech, U. of Virginia)
A new technical paper titled “Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache ...
Design-Reuse14d
Future Trends in SoC Interconnect
Design automation software can remove the need for expertise in self-timed design, enabling the on-chip interconnect to be treated as an additional IP block within a conventional (synchronous) design ...